Commit e39401e0b4 for qemu.org

commit e39401e0b4005389790bf847949c9e5950f5fa55
Author: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Date:   Wed Sep 30 02:00:56 2026 +0000

    target/alpha: prefix divs helper

    Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
    Link: https://lore.kernel.org/qemu-devel/20260930020108.217892-10-pierrick.bouvier@oss.qualcomm.com
    Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c
index 5b7e4bd5eb..529eadca9f 100644
--- a/target/alpha/fpu_helper.c
+++ b/target/alpha/fpu_helper.c
@@ -248,7 +248,7 @@ uint64_t helper_muls(CPUAlphaState *env, uint64_t a, uint64_t b)
     return float32_to_s(fr);
 }

-uint64_t helper_divs(CPUAlphaState *env, uint64_t a, uint64_t b)
+uint64_t helper_alpha_divs(CPUAlphaState *env, uint64_t a, uint64_t b)
 {
     float32 fa, fb, fr;

diff --git a/target/alpha/helper.h b/target/alpha/helper.h
index 954a5c8294..e2f0b96db7 100644
--- a/target/alpha/helper.h
+++ b/target/alpha/helper.h
@@ -47,7 +47,7 @@ DEF_HELPER_FLAGS_1(memory_to_s, TCG_CALL_NO_RWG_SE, i64, i32)
 DEF_HELPER_FLAGS_3(adds, TCG_CALL_NO_RWG, i64, env, i64, i64)
 DEF_HELPER_FLAGS_3(subs, TCG_CALL_NO_RWG, i64, env, i64, i64)
 DEF_HELPER_FLAGS_3(muls, TCG_CALL_NO_RWG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_RWG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(alpha_divs, TCG_CALL_NO_RWG, i64, env, i64, i64)
 DEF_HELPER_FLAGS_2(sqrts, TCG_CALL_NO_RWG, i64, env, i64)

 DEF_HELPER_FLAGS_3(addt, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index c66e3f9c14..ac57e4d262 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -790,7 +790,7 @@ static inline void glue(gen_, name)(DisasContext *ctx,                  \
 IEEE_ARITH3(adds)
 IEEE_ARITH3(subs)
 IEEE_ARITH3(muls)
-IEEE_ARITH3(divs)
+IEEE_ARITH3(alpha_divs)
 IEEE_ARITH3(addt)
 IEEE_ARITH3(subt)
 IEEE_ARITH3(mult)
@@ -2086,7 +2086,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
         case 0x03:
             /* DIVS */
             REQUIRE_FEN;
-            gen_divs(ctx, ra, rb, rc, fn11);
+            gen_alpha_divs(ctx, ra, rb, rc, fn11);
             break;
         case 0x20:
             /* ADDT */