Commit 06fbd15ea5 for qemu.org

commit 06fbd15ea5e1356adc06f59fdf89a0f68bfdd1cd
Merge: 56afd82bd4 9e0dff1dca
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Mon Nov 2 06:46:55 2026 -0800

    Merge tag 'pull-ppc-for-11.2-sf-20261102' of https://gitlab.com/harshpb/qemu into staging

    PPC PR for 11.2 Soft Freeze

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    # gpg: Signature made Mon 02 Nov 2026 03:13:31 AM PST
    # gpg:                using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
    # gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined]
    # gpg:                 aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined]
    # gpg: WARNING: This key is not certified with a trusted signature!
    # gpg:          There is no indication that the signature belongs to the owner.
    # Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D  2142 4544 E994 F9D6 8FBB

    * tag 'pull-ppc-for-11.2-sf-20261102' of https://gitlab.com/harshpb/qemu:
      pnv/phb5: Mask off LSI Source-ID based on number of interrupts
      pnv/phb5: Implement IODA PCT table
      pnv/phb5: Set link speed and width in the DLP training control register
      pnv/phb5: Set link-active status in HPSTAT and LMR registers
      pnv/phb5: Implement write-clear and return 1's on unimplemented reg read
      pnv/phb5: Implement read-only and write-only bits of registers
      pnv/phb5: Implement sticky reset logic in PHB5
      pnv/phb5: Add reset logic to PHB5
      qtest/phb5: Add testbench for PHB

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>