Commit 18b6303f49 for qemu.org

commit 18b6303f49c9d8ac6fdc90adea3438d84fefba1d
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Mon Sep 7 14:02:20 2026 +0100

    target/arm: Move ESR_EL1 definition to vmsa_pmsa_cp_reginfo

    Currently we define ESR_EL1 in vmsa_cp_reginfo[], but ESR_EL1 isn't
    VMSA specific.  This doesn't matter for "is the register visible when
    it should be?", because currently all our AArch64 CPUs are VMSA.  But
    it does matter for migration, because the DFSR definition in
    vmsa_pmsa_cp_reginfo[] is marked ARM_CP_ALIAS on the assumption that
    the migration of cp15.dfsr_ns will be handled by migrating esr_el[1],
    which is the same underlying field in the CPU state.

    Move ESR_EL1 to vmsa_pmsa_cp_reginfo[]; this will fix the lack of
    migration of DFSR for R-profile CPUs.  This is a migration break for
    those CPUs, but none of them are used in versioned machine types.

    (The S banked DFSR is already migrated, because we register ESR_EL3
    in el3_cp_reginfo[] if EL3 exists, regardless of whether we have VMSA
    or PMSA.)

    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20260907130223.3148989-6-peter.maydell@linaro.org

diff --git a/target/arm/helper.c b/target/arm/helper.c
index c2e9415363..5f930f6fa8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2894,6 +2894,14 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 }

 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
+    { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
+      .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_ESR_EL1,
+      .nv2_redirect_offset = 0x138 | NV2_REDIR_NV1,
+      .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 5, 2, 0),
+      .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 5, 2, 0),
+      .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS,
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
@@ -2918,14 +2926,6 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
 };

 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
-    { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
-      .access = PL1_RW, .accessfn = access_tvm_trvm,
-      .fgt = FGT_ESR_EL1,
-      .nv2_redirect_offset = 0x138 | NV2_REDIR_NV1,
-      .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 5, 2, 0),
-      .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 5, 2, 0),
-      .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,