Commit 295803fe2e for qemu.org
commit 295803fe2e648ca2ae420afb3953106678f18400
Author: Peter Maydell <peter.maydell@linaro.org>
Date: Tue Oct 20 13:27:50 2026 +0100
target/or1k: Convert to translate_for_debug
Convert or1k to providing the translate_for_debug method rather than
the deprecated get_phys_addr_debug method.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20261020122752.3651914-4-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c
index 5aba8a42a9..8537d1a032 100644
--- a/target/or1k/cpu.c
+++ b/target/or1k/cpu.c
@@ -247,7 +247,7 @@ static void openrisc_any_initfn(Object *obj)
static const struct SysemuCPUOps openrisc_sysemu_ops = {
.has_work = openrisc_cpu_has_work,
- .get_phys_addr_debug = openrisc_cpu_get_phys_addr_debug,
+ .translate_for_debug = openrisc_cpu_translate_for_debug,
};
#endif
diff --git a/target/or1k/cpu.h b/target/or1k/cpu.h
index 96ed1779fa..50a665eec0 100644
--- a/target/or1k/cpu.h
+++ b/target/or1k/cpu.h
@@ -298,7 +298,8 @@ void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,
int print_insn_or1k(bfd_vma addr, disassemble_info *info);
#ifndef CONFIG_USER_ONLY
-hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
+bool openrisc_cpu_translate_for_debug(CPUState *cpu, vaddr addr,
+ TranslateForDebugResult *result);
bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/or1k/mmu.c b/target/or1k/mmu.c
index 3fc56e1b77..a78e8c8ca2 100644
--- a/target/or1k/mmu.c
+++ b/target/or1k/mmu.c
@@ -139,7 +139,8 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
cpu_loop_exit_restore(cs, retaddr);
}
-hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)
+bool openrisc_cpu_translate_for_debug(CPUState *cs, vaddr addr,
+ TranslateForDebugResult *result)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
int prot, excp, sr = cpu->env.sr;
@@ -152,12 +153,15 @@ hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)
PAGE_READ,
(sr & SR_SM) != 0);
if (!excp) {
- return phys_addr;
+ break;
}
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
PAGE_EXEC,
(sr & SR_SM) != 0);
- return excp ? -1 : phys_addr;
+ if (excp) {
+ return false;
+ }
+ break;
default:
/* The mmu is partially enabled, and we don't really have
@@ -167,13 +171,20 @@ hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)
PAGE_EXEC | PAGE_READ | PAGE_WRITE,
(sr & SR_SM) != 0);
if (!excp) {
- return phys_addr;
+ break;
}
/* fallthru */
case 0:
/* The mmu is definitely disabled; lookups never fail. */
get_phys_nommu(&phys_addr, &prot, addr);
- return phys_addr;
+ break;
}
+
+ *result = (TranslateForDebugResult) {
+ .physaddr = phys_addr,
+ .lg_page_size = TARGET_PAGE_BITS,
+ .attrs.debug = 1,
+ };
+ return true;
}