Commit 2c0584588c for qemu.org

commit 2c0584588c9fedc2a8abc087c01a498ce80997d0
Merge: d731492832 59f954f827
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Tue Oct 27 06:08:01 2026 -0500

    Merge tag 'pbouvier/pr/multi_target-20261024' of https://gitlab.com/p-b-o/qemu into staging

    Changes:
    - [PATCH v2 00/11] multi-target: prefix helpers with target prefix (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>)
      Link: https://lore.kernel.org/qemu-devel/20261024163249.77855-1-pierrick.bouvier@oss.qualcomm.com
    - [PATCH v3 0/9] multi-target: add riscv64-softmmu (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>)
      Link: https://lore.kernel.org/qemu-devel/20261024061616.27381-1-pierrick.bouvier@oss.qualcomm.com

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    # gpg: Signature made Sat 24 Oct 2026 12:36:42 PM CDT
    # gpg:                using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
    # gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
    # gpg: WARNING: This key is not certified with a trusted signature!
    # gpg:          There is no indication that the signature belongs to the owner.
    # Primary key fingerprint: 37C1 5694 D8BA 9764 B197  3FDB B444 37D1 9C28 62DF

    * tag 'pbouvier/pr/multi_target-20261024' of https://gitlab.com/p-b-o/qemu:
      meson.build: list all remaining softmmu targets as comments
      meson.build: add riscv64-softmmu to multi-target
      target/riscv/kvm: restrict kvm-accel-riscv-cpu to riscv targets
      target/riscv/tcg: restrict tcg-accel-riscv-cpu to riscv targets
      target/riscv: rename virt_acpi_setup to riscv_virt_acpi_setup
      hw/riscv/virt: restrict scope of virt_is_acpi_enabled to this file
      test/unit/multi-target: check QOM types can be initialized with any target
      hw/riscv/virt: make machine available for riscv targets only
      target-info: add target_base_riscv
      target/tricore: remove explicit target specific prefix
      target/rx: remove explicit target specific prefix
      target/or1k: remove explicit target specific prefix
      target/microblaze: remove explicit target specific prefix
      target/hppa: remove explicit target specific prefix
      target/hexagon: remove explicit target specific prefix
      target/alpha: remove explicit target specific prefix
      tcg: prefix helpers with target base architecture
      target/sparc: define crypto helpers using HELPER macro
      tcg: introduce HELPER_INFO macro
      target/rx: define and call helpers using HELPER macro

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>