Commit 37ed2ff635 for qemu.org

commit 37ed2ff635774f7529acc249f6ad6be113ae41ef
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Mon Sep 7 14:02:22 2026 +0100

    target/arm: Don't register 64-bit TTBR0, TTBR1 for PMSA

    We register the 64-bit versions of TTBR0 and TTBR1 in
    lpae_cp_reginfo[], marking them as ARM_CP_ALIAS because the AArch64
    definitions in vmsa_cp_reginfo[] will handle their migration.

    However, this means that we are also defining these registers as
    present in the Cortex-R52, which is a v8R PMSA CPU.  v8R does define
    AMAIR0, AMAIR1 and the PAR, but does not have TTBR0 or TTBR1.

    Split the TTBR0 and TTBR1 definitions into a new lpae_vmsa_cp_reginfo
    which we only register when we have both LPAE and VMSA.

    This is a migration break for Cortex-R52 CPUs (which we don't use in
    any versioned machine type).

    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20260907130223.3148989-8-peter.maydell@linaro.org

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5f930f6fa8..1fe06a6351 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3098,6 +3098,9 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
                              offsetof(CPUARMState, cp15.par_ns)} },
+};
+
+static const ARMCPRegInfo lpae_vmsa_cp_reginfo[] = {
     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
@@ -7226,6 +7229,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
     if (arm_feature(env, ARM_FEATURE_LPAE)) {
         define_arm_cp_regs(cpu, lpae_cp_reginfo);
+        if (!arm_feature(env, ARM_FEATURE_PMSA)) {
+            define_arm_cp_regs(cpu, lpae_vmsa_cp_reginfo);
+        }
     }
     if (cpu_isar_feature(aa32_jazelle, cpu)) {
         define_arm_cp_regs(cpu, jazelle_regs);