Commit 38fd707591 for qemu.org

commit 38fd70759197680de4f15a0dd0272231e4fe1d7e
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date:   Tue Sep 15 09:30:46 2026 -0700

    tests/tcg/hexagon: add scalar+HVX and masked store tests

    Test a packet with both a scalar store and an HVX store, and test
    a non-inverted masked store (if (q0) vmem) to verify the invert=false
    path in masked store generation.

    Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
    Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c
index f20afc8e67..0285886c2a 100644
--- a/tests/tcg/hexagon/hvx_misc.c
+++ b/tests/tcg/hexagon/hvx_misc.c
@@ -566,6 +566,69 @@ void test_store_new()
     check_output_w(__LINE__, 1);
 }

+/*
+ * Test a packet with both a scalar store and an HVX store.
+ */
+static uint32_t scalar_store_dst;
+
+static void test_scalar_hvx_store(void)
+{
+    scalar_store_dst = 0;
+    memset(&expect[0], 0, sizeof(MMVector));
+
+    /* Fill v0 with 0xABCD pattern */
+    for (int i = 0; i < MAX_VEC_SIZE_BYTES / 4; i++) {
+        expect[0].uw[i] = 0xABCDABCD;
+    }
+
+    asm("r0 = #0xABCDABCD\n\t"
+        "v0 = vsplat(r0)\n\t"
+        "r1 = #42\n\t"
+        "{\n\t"
+        "    memw(%[scalar]) = r1\n\t"
+        "    vmem(%[hvx]) = v0\n\t"
+        "}\n\t"
+        :
+        : [scalar] "r"(&scalar_store_dst),
+          [hvx] "r"(&output[0])
+        : "r0", "r1", "v0", "memory");
+
+    check_output_w(__LINE__, 1);
+    if (scalar_store_dst != 42) {
+        printf("ERROR at line %d: scalar_store_dst = %d, expected 42\n",
+               __LINE__, scalar_store_dst);
+        err++;
+    }
+}
+
+/*
+ * Test non-inverted masked store: if (Qv) vmem(Rt) = Vs.
+ * Existing tests only cover the inverted form (!Qv).
+ * Use an all-true Q predicate to unconditionally store.
+ */
+static void test_masked_store_noninvert(void)
+{
+    void *p0 = buffer0;
+    void *pout = output;
+
+    memset(&output[0], 0xff, sizeof(MMVector));
+
+    for (int i = 0; i < MAX_VEC_SIZE_BYTES / 4; i++) {
+        expect[0].uw[i] = buffer0[0].uw[i];
+    }
+
+    asm("v5 = vmem(%[src] + #0)\n\t"
+        "r0 = #-1\n\t"
+        "v6 = vsplat(r0)\n\t"
+        "q0 = vand(v6, r0)\n\t"
+        "if (q0) vmem(%[dst]) = v5\n\t"
+        :
+        : [src] "r"(p0), [dst] "r"(pout)
+        : "r0", "v5", "v6", "q0", "memory");
+
+    check_output_w(__LINE__, 1);
+}
+
 int main()
 {
     init_buffers();
@@ -615,6 +678,9 @@ int main()

     test_store_new();

+    test_scalar_hvx_store();
+    test_masked_store_noninvert();
+
     puts(err ? "FAIL" : "PASS");
     return err ? 1 : 0;
 }