Commit 5716c297dd for openssl.org

commit 5716c297ddadfa332147c4da5155f0fe3b598167
Author: SY-David <jianao931212@gmail.com>
Date:   Tue Nov 3 20:52:21 2026 +0800

    crypto/armcap.c: enable Neon Montgomery multiplication on Cortex-A76

    Cortex-A76 uses CPU part number 0xD0B[1].  Define that part number
    and add it to the existing Cortex-A72/Neoverse-N1 model check
    in arm64_setup_rsa_neonized().

    [1] https://support.arm.com/documentation/100798/0401/AArch64-System-registers/MIDR-EL1--Main-ID-Register--EL1

    Assisted-by: Codex:GPT-5.6 Sol Extra High
    Reviewed-by: Paul Dale <paul.dale@oracle.com>
    Reviewed-by: Nikola Pajkovsky <nikolap@openssl.org>
    Reviewed-by: Eugene Syromiatnikov <esyr@openssl.org>
    Merge-date: Fri Nov  6 10:55:51 2026
    Merged-from: https://github.com/openssl/openssl/pull/33515

diff --git a/crypto/armcap.c b/crypto/armcap.c
index 13acb257a3..8388b8ed8d 100644
--- a/crypto/armcap.c
+++ b/crypto/armcap.c
@@ -262,6 +262,7 @@ static inline void arm64_setup_rsa_neonized(void)

     if ((OPENSSL_armcap_P & ARMV7_NEON)
         && (MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
+            || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
             || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N1)))
         OPENSSL_armv8_rsa_neonized = 1;
 }
diff --git a/include/arch/arm_arch.h b/include/arch/arm_arch.h
index 0721b067f7..59fa554414 100644
--- a/include/arch/arm_arch.h
+++ b/include/arch/arm_arch.h
@@ -103,6 +103,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
 #define ARM_CPU_IMP_NVIDIA 0x4E

 #define ARM_CPU_PART_CORTEX_A72 0xD08
+#define ARM_CPU_PART_CORTEX_A76 0xD0B
 #define ARM_CPU_PART_N1 0xD0C
 #define ARM_CPU_PART_V1 0xD40
 #define ARM_CPU_PART_N2 0xD49