Commit 62c31d1b6a for qemu.org

commit 62c31d1b6aa8e255c528df41c51a35dec9516be9
Merge: b11de76e08 bfdd4f6a91
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Fri Oct 16 06:09:05 2026 +0200

    Merge tag 'pull-riscv-to-apply-20261016' of https://github.com/alistair23/qemu into staging

    RISC-V PR for 11.2

    * Check G-stage write permission for VS-stage A/D updates
    * Restore LCOFI handling in interrupt CSRs
    * Fix csrrs disasembly decoding
    * Stop translating after WFI
    * Raise virtual instruction exception on svinval instructions
    * Fix some KVM migration issues
    * Add support for Milk-V Duo board
    * Make MIP accesses atomic and BQL-safe
    * Add initial sdext support
    * Add SiFive Xsfvqmaccdod/Xsfvqmaccqoq int8 matmul extensions
    * Add the Server Platform Reference Board
    * Revert invalidate reservations after stores for linux user
    * Fix the UART register width in SPCR
    * Check Svnapot PTE before updating A/D bits
    * Add Tenstorrent Atlantis PRCM model
    * Fix RV32 fixed counter accesses
    * Write back fsgnjn.h and fsgnjx.h results
    * Ensure Zcmt jvt.mode is WARL

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    * tag 'pull-riscv-to-apply-20261016' of https://github.com/alistair23/qemu: (50 commits)
      target/riscv: normalize Zcmt jvt.mode on writes
      target/riscv: write back fsgnjn.h and fsgnjx.h results
      target/riscv: fix RV32 fixed counter accesses
      hw/riscv/tt-atlantis: Update UART and I2C to use clk from PRCM
      hw/riscv/tt-atlantis: Add PRCMs to tt-atlantis model
      hw/misc: Add Tenstorrent Atlantis PRCM model
      target/riscv: Check Svnapot PTE before updating A/D bits
      tests/qtest/bios-tables-test: Update riscv64 virt SPCR golden reference
      hw/riscv/virt-acpi-build: Fix the UART register width in SPCR
      tests/qtest/bios-tables-test: Allow changes to riscv64 virt SPCR
      Revert "linux-user/riscv: invalidate reservations after stores"
      docs: add riscv-server-ref.rst
      tests/functional/riscv64: add riscv-server-ref tests
      hw/riscv: server platform reference machine
      target/riscv: add riscv-server-ref CPU
      target/riscv/cpu.c: remove 'bare' condition for .profile
      tests/tcg/riscv64: Add tests for SiFive int8 matmul extensions
      disas/riscv: Add disassembler support for Xsfvqmaccdod/Xsfvqmaccqoq
      target/riscv: rvv: Add SiFive custom int8 matmul instructions
      target/riscv/cpu: Add SiFive custom int8 matmul extension implied rules
      ...

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>