Commit 80c1d80c10 for qemu.org
commit 80c1d80c10a0676728d65874a9641eb578626d7c
Merge: 3876503faf 443fe4436f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Thu Sep 24 19:35:55 2026 -0700
Merge tag 'pull-hex-20260924' of https://github.com/qualcomm/qemu into staging
Hexagon: HVX sysemu, tests, fixes
Added HVX support for system emulation: bind SSR.XA to the associated
HVX context.
Endian bugfixes for HVX.
Add tests for improved coverage.
Improvements in the simple packet short-circuit logic - for handling
multiple reg-writes to GPRs, System, Guest, Vector, Vec-Pred registers.
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# gpg: Signature made Thu 24 Sep 2026 06:53:49 PM PDT
# gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown]
# gpg: aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain <bcain@kernel.org>" [unknown]
# gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg: aka "bcain" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47
# Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32
* tag 'pull-hex-20260924' of https://github.com/qualcomm/qemu: (40 commits)
target/hexagon: rename LEN to OFFS_REG_END in VTCM macros
tests/tcg/hexagon: check the two HVX predicate build paths agree
target/hexagon: fix HVX predicate save size for histogram ops
tests/tcg/hexagon: add vgather/vscatter region-length tests
target/hexagon: fix HVX scatter/gather region-length check
target/hexagon: fix HVX big-endian byte access
tests/functional/hexagon: add HVX tests
target/hexagon: share HVX contexts among CPUs
target/hexagon: prepare for separate HVX contexts
target/hexagon: raise an exception for HVX with SSR:XE clear
tcg: split out _var forms of gvec saturating/mul/shift-immediate ops
tcg: add base arguments to the gvec 2s, dup_i32 and cmp expanders
tcg: split out _var forms of gvec logical, abs and min/max ops
tests/tcg/hexagon: add decbin MPS test case
tests/tcg/hexagon: add scalar+HVX and masked store tests
tests/tcg/hexagon: add rounding conv, sffma:lib, and sfinvsqrta
tests/tcg/hexagon: add predicate register transfer test
tests/tcg/hexagon: add unconditional store-immediate tests
tests/tcg/hexagon: add dfmpyhh
tests/tcg/hexagon: add sfrecipa edge case tests
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>