Commit 940f5e6f3e for qemu.org
commit 940f5e6f3ea91e6ac59544c054e4c221902dd30d
Merge: d5b5083cb7 512b062991
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Thu Oct 15 13:13:17 2026 +0200
Merge tag 'pull-tcg-20261015' of https://gitlab.com/rth7680/qemu into staging
tcg: Introduce tcg_type_bits() helper
tcg/riscv64: Remove vector min/max ops with immediates
tcg/optimize: Do not derive s_mask from rotated s_mask
tcg/aarch64/tcg-target.c.inc: Correct register MIN/MAX instuctions
tcg/riscv64: Validate AUIPC relocation range
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* tag 'pull-tcg-20261015' of https://gitlab.com/rth7680/qemu:
tcg/riscv64: Fall back when AUIPC pairs are out of range
tcg/riscv64: Validate AUIPC relocation range
tcg/riscv64: Fix off-by-one in branch range tests
tcg/riscv64: Return success from encode_bimm
tcg/riscv64: Return success from encode_jimm
tcg/riscv64: Assert immediate in range for {i,s,u,vi}-type insns
tcg/riscv64: Adjust sign of lui immediate in tcg_out_movi
tcg/riscv64: Use signed type for encoding immediates
tcg/riscv64: Rename uj-type to j-type format
tcg/riscv64: Rename sb-type to b-type format
tcg/riscv64: Return tcg_insn_unit from insn encoders
tcg: Introduce tcg_type_bits() helper
tcg/riscv64: Remove vector min/max ops with immediates
tcg/aarch64/tcg-target.c.inc: Correct register MIN/MAX instuctions
tests/tcg: Add tests for sign extension after rotate
tcg/optimize: Do not derive s_mask from rotated s_mask
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>