Commit 9537951f87 for qemu.org
commit 9537951f875b7a54ddfdd922b82579ef36337b07
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Sun Sep 13 22:20:25 2026 +0000
tcg/riscv64: Return success from encode_bimm
Centralize the range test for this encoding.
Directly OR into the insn value.
Assert success in encode_b.
Reviewed-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc
index c8f91612d3..e4e1ce91ea 100644
--- a/tcg/riscv64/tcg-target.c.inc
+++ b/tcg/riscv64/tcg-target.c.inc
@@ -474,22 +474,25 @@ static tcg_insn_unit encode_s(RISCVInsn opc, TCGReg rs1,
/* Type-B */
-static tcg_insn_unit encode_bimm12(tcg_target_long imm)
+static bool encode_bimm12(tcg_insn_unit *insn, tcg_target_long imm)
{
- tcg_insn_unit ret = 0;
-
- ret |= (imm & 0x1000) << 19;
- ret |= (imm & 0x7e0) << 20;
- ret |= (imm & 0x1e) << 7;
- ret |= (imm & 0x800) >> 4;
-
- return ret;
+ if ((imm & 1) == 0 && imm == sextract32(imm, 0, 12)) {
+ *insn |= ((imm & 0x1000) << 19
+ | (imm & 0x7e0) << 20
+ | (imm & 0x1e) << 7
+ | (imm & 0x800) >> 4);
+ return true;
+ }
+ return false;
}
static tcg_insn_unit encode_b(RISCVInsn opc, TCGReg rs1,
TCGReg rs2, tcg_target_long imm)
{
- return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_bimm12(imm);
+ tcg_insn_unit insn = opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
+ bool ok = encode_bimm12(&insn, imm);
+ tcg_debug_assert(ok);
+ return insn;
}
/* Type-U */
@@ -623,12 +626,7 @@ static bool reloc_bimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
tcg_debug_assert((offset & 1) == 0);
- if (offset == sextreg(offset, 0, 12)) {
- *src_rw |= encode_bimm12(offset);
- return true;
- }
-
- return false;
+ return encode_bimm12(src_rw, offset);
}
static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target)