Commit 9a546e036a for qemu.org

commit 9a546e036a11fe1f634801eb75ec12fa238fb5ec
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date:   Sat Sep 26 19:43:43 2026 -0700

    target/hexagon: emit explicit TCG memory barriers

    Generate release barriers before release and HVX scatter-release
    operations, acquire barriers after acquire loads, and full barriers
    for barrier, syncht, isync, and dmsyncht.

    Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
    Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 6715758bfa..cd1abdf146 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -836,12 +836,27 @@ static void mark_store_width(DisasContext *ctx)

 static void gen_insn(DisasContext *ctx)
 {
+    uint16_t opcode = ctx->insn->opcode;
+
+    if (GET_ATTRIB(opcode, A_RELEASE) ||
+        GET_ATTRIB(opcode, A_CVI_SCATTER_RELEASE)) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+    }
+
     if (ctx->insn->generate) {
         ctx->insn->generate(ctx);
         mark_store_width(ctx);
     } else {
         hex_gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE);
     }
+
+    if (GET_ATTRIB(opcode, A_ACQUIRE)) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+    }
+    if (opcode == Y2_barrier || opcode == Y2_syncht ||
+        opcode == Y2_isync || opcode == Y6_dmsyncht) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+    }
 }

 /*