Commit bfdd4f6a91 for qemu.org

commit bfdd4f6a918ffad4f013d4f53a9adca1adc0aa3b
Author: wangyang <wangyang25@otcaix.iscas.ac.cn>
Date:   Fri Sep 4 09:26:08 2026 +0800

    target/riscv: normalize Zcmt jvt.mode on writes

    Only jvt.mode=0 is implemented by QEMU. write_jvt() currently retains
    reserved mode bits, so a legal WARL write of base|1 is read back
    unchanged and causes a subsequent cm.jt to trap. Mask the write with
    JVT_BASE to normalize the unsupported mode.

    Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4408
    Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Message-ID: <a64897d07c6b0c61451cd5382afafcd27201367d.20260904092608.git.wangyang25.otcaix.iscas.ac.cn>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 64be8ca309..063590f56a 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -6086,7 +6086,7 @@ static RISCVException read_jvt(CPURISCVState *env, int csrno,
 static RISCVException write_jvt(CPURISCVState *env, int csrno,
                                 target_ulong val, uintptr_t ra)
 {
-    env->jvt = val;
+    env->jvt = val & JVT_BASE;
     return RISCV_EXCP_NONE;
 }