Commit c05d7690a2 for qemu.org

commit c05d7690a2b6ce861450e6b26bded7748f5a4efc
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date:   Wed Oct 7 17:37:04 2026 -0700

    target/hexagon: fix V6_vcmov reserved-bit encoding

    The architecture defines this encoding bit as zero.  Leaving it
    unconstrained accepts reserved encodings as V6_vcmov.

    Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
    Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def
index 084ae3d854..b46f51492d 100644
--- a/target/hexagon/imported/mmvec/encode_ext.def
+++ b/target/hexagon/imported/mmvec/encode_ext.def
@@ -394,7 +394,7 @@ DEF_ENC(V6_vshuff,             ICLASS_CJ" 1 001 111 ttttt PP 1 yyyyy 001 xxxxx")
 DEF_ENC(V6_vdeal,             ICLASS_CJ" 1 001 111 ttttt PP 1 yyyyy 010 xxxxx") //

 DEF_FIELDROW_DESC32(    ICLASS_CJ" 1 010 --- ----- PP - ----- ----- ---","[#2] if (Ps) Vd=Vu")
-DEF_ENC(V6_vcmov,         ICLASS_CJ" 1 010 000 ----- PP - uuuuu -ss ddddd")
+DEF_ENC(V6_vcmov,         ICLASS_CJ" 1 010 000 ----- PP 0 uuuuu -ss ddddd")
 DEF_ENC(V6_vncmov,         ICLASS_CJ" 1 010 001 ----- PP - uuuuu -ss ddddd")
 DEF_ENC(V6_vnccombine,     ICLASS_CJ" 1 010 010 vvvvv PP - uuuuu -ss ddddd")
 DEF_ENC(V6_vccombine,     ICLASS_CJ" 1 010 011 vvvvv PP - uuuuu -ss ddddd")