Commit c0b1b7c987 for qemu.org

commit c0b1b7c987229ef85cca9118509343c0bafe39bb
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Fri Sep 25 14:49:59 2026 -0700

    target/arm: Widen cpsr_{read, write}_for_spsr_elx to uint64_t

    We will shortly need to handle bit 36: PSTATE.UINJ.

    Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20260925215004.456336-10-richard.henderson@linaro.org
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 76956cfd97..f843f281fc 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9514,9 +9514,9 @@ static int aarch64_regnum(CPUARMState *env, int aarch32_reg)
     }
 }

-uint32_t cpsr_read_for_spsr_elx(CPUARMState *env)
+uint64_t cpsr_read_for_spsr_elx(CPUARMState *env)
 {
-    uint32_t ret = cpsr_read(env);
+    uint64_t ret = cpsr_read(env);

     /* Move DIT to the correct location for SPSR_ELx */
     if (ret & CPSR_DIT) {
@@ -9529,7 +9529,7 @@ uint32_t cpsr_read_for_spsr_elx(CPUARMState *env)
     return ret;
 }

-void cpsr_write_from_spsr_elx(CPUARMState *env, uint32_t val)
+void cpsr_write_from_spsr_elx(CPUARMState *env, uint64_t val)
 {
     uint32_t mask;

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1efda54327..843e12487e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -2016,8 +2016,8 @@ void vfp_clear_float_status_exc_flags(CPUARMState *env);
  */
 void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask);
 bool arm_pan_enabled(CPUARMState *env);
-uint32_t cpsr_read_for_spsr_elx(CPUARMState *env);
-void cpsr_write_from_spsr_elx(CPUARMState *env, uint32_t val);
+uint64_t cpsr_read_for_spsr_elx(CPUARMState *env);
+void cpsr_write_from_spsr_elx(CPUARMState *env, uint64_t val);

 /* Compare uint64_t for qsort and bsearch. */
 int compare_u64(const void *a, const void *b);