Commit d60f2b9342 for qemu.org

commit d60f2b934245eba3428393168adb5b5f0dccc4ee
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Thu Oct 22 20:59:24 2026 +0100

    hw/net/can/flexcan: Fix FLEXCAN_CRCR_MBCRC definition

    FLEXCAN_CRC_MBCRC is defined as
      (((x) & FLEXCAN_CRCR_MBCRC_MASK) << 16)
    but FLEXCAN_CRCRC_MBCRC_MASK is (like the other _MASK values
    in this header) defined to be an in-place mask
     FLEXCAN_GENMASK(22, 16)
    (a value with bits set from 16 to 22).  The mask and shift operations
    are done in the wrong order, and so the result of the macro can only
    ever be zero.

    Fix the macro to shift first and mask second.

    Cc: qemu-stable@nongnu.org
    Fixes: 3c4e23cbb597 ("hw/net/can/flexcan: NXP FlexCAN core emulation")
    Resolves: Coverity CID 1662973
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Matyas Bobek <matyas.bobek@gmail.com>
    Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
    Message-ID: <20261022195924.672606-1-peter.maydell@linaro.org>
    Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

diff --git a/hw/net/can/flexcan_regs.h b/hw/net/can/flexcan_regs.h
index c18bc4736e..7923bf836f 100644
--- a/hw/net/can/flexcan_regs.h
+++ b/hw/net/can/flexcan_regs.h
@@ -150,7 +150,7 @@

 /* FLEXCAN CRC Register (CRCR) bits */
 #define FLEXCAN_CRCR_MBCRC_MASK         FLEXCAN_GENMASK(22, 16)
-#define FLEXCAN_CRCR_MBCRC(x)           (((x) & FLEXCAN_CRCR_MBCRC_MASK) << 16)
+#define FLEXCAN_CRCR_MBCRC(x)           (((x) << 16) & FLEXCAN_CRCR_MBCRC_MASK)
 #define FLEXCAN_CRCR_TXCRC_MASK         FLEXCAN_GENMASK(14, 0)
 #define FLEXCAN_CRCR_TXCRC(x)           ((x) & FLEXCAN_CRCR_TXCRC_MASK)