Commit ec65e16fd2 for qemu.org

commit ec65e16fd2ba012d57b1bbfcfcd04c31c4111924
Author: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Date:   Sat Oct 24 06:16:12 2026 +0000

    target/riscv/tcg: restrict tcg-accel-riscv-cpu to riscv targets

    $ ./build/tests/unit/test-multi-target
    Type 'tcg-accel-riscv-cpu' is missing its parent 'accel-riscv-cpu'
    Aborted

    Parent type is conditionally registered from current target:
    register_accel_target_type uses '"accel-" + target_cpu_type()' as type
    name. Multi-target test takes the first target available, which is not
    riscv in current state.

    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Acked-by: Alistair Francis <alistair.francis@wdc.com>
    Link: https://lore.kernel.org/qemu-devel/20261024061616.27381-7-pierrick.bouvier@oss.qualcomm.com
    Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 80c0463617..cbff18afb5 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1748,6 +1748,7 @@ static const TypeInfo riscv_tcg_cpu_accel_type_info = {

     .parent = TYPE_ACCEL_CPU,
     .class_init = riscv_tcg_cpu_accel_class_init,
+    .is_available = target_base_riscv,
     .abstract = true,
 };