Commit fe131396af for qemu.org

commit fe131396afb0fc01724ec161b66b2cd49620241a
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Fri Jul 31 11:56:27 2026 -0700

    target/s390x/tcg: Simplify LRVR

    If we drop TCG_BSWAP_IZ, we don't need to zero-extend r1 on input.
    Since the output gets passed to deposit in wout_r1_32, the high
    bits of the bswap output need not have any specific value, so we
    can drop TCG_BSWAP_OZ.

    Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    Message-ID: <20260731185628.23161-15-richard.henderson@linaro.org>

diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 854ec37d30..68260ffd9d 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -588,7 +588,7 @@
     F(0xb340, LPXBR,   RRE,   Z,   x2h, x2l, new_P, x1_P, absf128, f128, IF_BFP)
     F(0xb370, LPDFR,   RRE,   FPSSH, 0, f2, new, f1, absf64, 0, IF_AFP1 | IF_AFP2)
 /* LOAD REVERSED */
-    C(0xb91f, LRVR,    RRE,   Z,   0, r2_32u, new, r1_32, rev32, 0)
+    C(0xb91f, LRVR,    RRE,   Z,   0, r2_o, new, r1_32, rev32, 0)
     C(0xb90f, LRVGR,   RRE,   Z,   0, r2_o, r1, 0, rev64, 0)
     D(0xe31f, LRVH,    RXY_a, Z,   0, a2, new, r1_16, ld, 0, MO_LEUW)
     D(0xe31e, LRV,     RXY_a, Z,   0, a2, new, r1_32, ld, 0, MO_LEUL)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 0449fc2cee..a4374bd41f 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -3715,7 +3715,7 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)

 static DisasJumpType op_rev32(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_bswap32_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+    tcg_gen_bswap32_i64(o->out, o->in2, 0);
     return DISAS_NEXT;
 }